1. Field of the Invention
The present invention relates to switched capacitor converters and, more particularly, to a high resolution, high speed, low power switched capacitor digital to analog converter (DAC).
2. Description of the Related Art
A switched capacitor analog to digital converter (ADC) operated according to the known SAR (Successive Approximation Register) technique comprises a plurality of weighted capacitors with associated switches and a local DAC. The capacitors are charged by a voltage sample of an analog signal to be converted. The voltage sample is compared with an analog signal generated by the local DAC. Typically, the same weighted capacitors are used both for the ADC and for the local DAC. If the comparison does not result in a coincidence, the local analog signal is changed to reduce the difference between the compared quantities. The comparison is repeated until the local analog signal is equal, within the limits of the converter accuracy, to the sampled analog signal. In this equality condition, the digital value of the local DAC is the digital output of the ADC corresponding to the input voltage sample.
Designing switched capacitor converters having high speed and high resolution in an integrated circuit requires facing problems of silicon area and accuracy. A SAR type switched capacitor converter comprises at least one array of binary weighted capacitors, with each capacitor being associated with a bit of the input code. A 10 bit DAC would require 1024 capacitors having a capacitance distribution according to the power of 2. Since the area of the smallest capacitor cannot be lower than a minimum area determined by the accuracy and linearity conditions set for the converter, each capacitor array would require an unacceptably large amount of silicon area.
To overcome this limitation, it is known to design converters comprising capacitor arrays split into two or more segments, with each segment comprising an array of independently weighted capacitors. In the case of two segments, the first segment is associated with the least significant bits (LSBs) of the digital input code and a second segment is associated with the most significant bits (MSBs) of the digital input code.
Various approaches are known for implementing DACs with segmented weighted capacitor arrays, as shown for example in FIGS. 1, 2 and 3.
FIG. 1 shows a DAC weighted capacitor array having a first segment, indicated as the xe2x80x9cupper arrayxe2x80x9d, formed of five capacitors with binary coded weights, i.e. with capacitances varying according to a factor 2i, where i varies from 0 to 4. The capacitors are indicated by their capacitances C, 2C, 4C, 8C and 16C, where C is preferably a predetermined unit capacitance. An electrode of each of the five capacitors is connected to a common node NSU and another electrode is connected, through a corresponding two-way switch of a group SWU of five switches, to a first or to a second reference voltage terminal VREFP, VREFM. The common node NSU is connected to a circuit 5 which detects and processes the analog signal output from the DAC. The switches SWU are set in one or the other position according to the values of the five most significant bits of a digital 8 bits input code A0-7. A second segment, indicated as xe2x80x9clower arrayxe2x80x9d is a resistive voltage divider formed of eight equal resistors R0-R7 connected in series between the terminals VREFP, VREFM of a voltage reference generator (not shown). The seven divider taps and the terminal VREFM can be connected to a common node NSL through an eight-way switch SWL controlled by three bits of the digital input code A0-7. The common node NSL is connected to the common node NSU of the upper array through a coupling capacitor Cs.
As is known to any person skilled in the art the switches SWU and SWL are preferably implemented as electronic switching arrangements comprising MOS transistors and/or pass-gates.
The DAC of FIG. 1 can be operated at a high speed and at a satisfactory accuracy, but has a high power consumption because the divider is permanently connected to the reference voltage generator. Furthermore, the reference voltage generator must be specifically designed to drive resistive loads and not only capacitive loads and therefore is per se a power consuming component.
Another known two-segment DAC, as shown in FIG. 2, is formed of an upper array identical to the upper array of FIG. 1 and a lower array which is formed as a weighted capacitor array similar to the upper array. In the example shown the lower array comprises three capacitors CL0, CL1, CL2, with binary coded weights having capacitances ranging from capacitance C associated with the least significant bit to 4C of the most significant bit. An electrode of each of the three capacitors is connected to a common node NSL and another electrode is connected selectively, through a corresponding two-way switch of a group SWL of three switches SWL0, SWL1, SWL2, either to the first or to the second reference voltage terminal VREFP, VREFM.
The upper array comprises five capacitors CU3, CU4, CU5, CU6, CU7 with binary coded weights having capacitances ranging from capacitance C associated with the least significant bit of the upper array to 16C of the most significant bit. An electrode of each of the five capacitors is connected to a common node NSU and another electrode is connected selectively, through a corresponding two-way switch of a group SWU of five switches SWU3, SWU4, SWU5, SWU6, SWU7, alternatively to the first second reference voltage terminals VREFP, VREFM.
A correction capacitor Cc having a capacitance equal to the least significant bit capacitance C is connected between node NSL and a reference voltage terminal, in this example ground. The correction capacitor is used, as known, to obtain that the sum of the capacitances in the array is exactly twice the capacitance of the capacitor associated with the most significant bit of the array. The two segments are coupled to one another through a coupling capacitor Cs having a capacitance selected as explained further below. The switches of the upper and lower array are controlled by an eight bit digital input code received from lines A0-7.
In the operation the contributions of the switched capacitors CL0, CL1, CL2 to the voltage at the common node NSL are scaled by the series coupling capacitor Cs and transferred to the common node NSU of the upper array.
This approach has the advantage of a low power consumption and does not require a specific voltage reference generator since all the loads are capacitive loads, however it is critical in the design because the conversion linearity is determined by the accuracy of the capacitance of the coupling capacitor Cs. It is known that this capacitance must be so selected that the capacitance resulting from the series connection of the coupling capacitor and the capacitance of the parallel connection of the capacitors of the lower array is equal to the capacitance of the smallest capacitor of the upper array. In the example shown Cs=8/7C=1.142857C, where C is the unit capacitance, or the capacitance of the smallest capacitor of the array. It is difficult to manufacture the coupling capacitor Cs with the necessary accuracy in many practical cases, in particular when the number of bits to be encoded in the lower array is high. This is a severe limitation for the use of this approach in high resolution converters. In this connection it should be noted that a complex capacitor array in an integrated circuit can be implemented efficiently by the use of a capacitor modular unit, i.e. a capacitor having a predetermined unit capacitance. According to this technique, each capacitor is made up of an integer number of modular units. This approach makes it possible to obtain maximum accuracy and matching. However, the coupling capacitor Cs in general cannot be formed by an integer number of modular units and therefore cannot be designed with the desired accuracy.
A known arrangement for overcoming the limitations of the converter according to FIG. 2 uses an operational amplifier to decouple the lower array from the coupling capacitor Cs, as shown in FIG. 3. To obtain a satisfactory conversion linearity it is necessary either that the operational amplifier has a low offset, or that a suitable circuit arrangement is provided to cancel the offset. A disadvantage of this approach is a limitation of the frequency band due to the limited pass-band of the operational amplifier and an increase of the power consumption and noise due to the presence of the operational amplifier.
An embodiment of the present invention provides an improved two-segment switched capacitor digital to analog converter. The embodiment provides a two-segment switched capacitor digital to analog converter formed of capacitors which can be designed with a high accuracy. The two-segment switched capacitor digital to analog converter is operable at a high speed and has a low power consumption.
An embodiment of the invention is a switched capacitor digital to analog converter including:
a first converter segment having a first array of binary weighted capacitors, the capacitances of which are integer multiples of a predetermined unit capacitance, each of said capacitors having a first electrode connected to a first common node and a second electrode connected through respective controllable switching means to either one of a first and second reference voltage terminals;
a second converter segment having a second array of binary weighted capacitors, the capacitances of which are integer multiples of said predetermined unit capacitance, each of the capacitors of the second converter segment having a first electrode connected to a second common node and a second electrode connected through respective controllable switching means to either one of said first and second reference voltage terminals;
a coupling capacitor with a first electrode connected to the first common node and a second electrode connected to the second common node;
control means coupled to the controllable switching means of the first and second converter segments to open or close selectively the connections to the first and second reference voltage terminals depending on the binary values of the bits of the digital input code;
an output terminal connected to the second common node for providing the analog output signal as a function of the digital input code; and
capacitance means connected between the first common node and at least one reference voltage terminal;
the coupling capacitor and the capacitance means being so selected that their capacitances, Cs and CATT respectively, substantially satisfy the following relationship: (2pxe2x88x921)xc2x7Csxe2x88x92CATT=2pxc2x7C, where p is the number of bits coded in the first converter segment and C is the unit capacitance.